A low noise amplifier is designed and simulated for the frequency range of 3.1 to 10.6 GHz using CMOS 0.18 µm technology. In this design there is a common source stage with an inductor in the source in order to reduce the amount of noise. The second stage is a structure to reuse the current in order to increase the gain and decrease the power consumption. Moreover, an NMOS transistor is used to improve the linearity of the proposed circuit. The proposed design is then simulated using the 0.18 µm CMOS technology in ADS software. The results show a noise level of less than 3dB and a flat gain of 14dB, also the IIP3 factor of the circuit is measured to be 0.5dBm which indicates the high degree of linearity in the circuit. The circuit power consumption is 23 mw.
