Implementing a new Torus network with intra-chip encryption

Azath Mubarakali, Dinesh Mavaluru, Jayabrabu Ramakrishnan


In recent years, the ad hoc network has emerged as a solution to the challenges of designing high-performance complex systems at the nanoscale. Maintaining information security in complex systems is an important issue. Therefore, this paper presents a new topology based on the Torres network with encryption capability to build internal network interfaces on the chip with tens or even hundreds of processor units considering the need for information security. The main platform for inter-chip communication is the PRDT network (2.1) and the basic encryption algorithm, RC6. Designing a new node and modifying the source and switched source network PRDT (2,1) encrypts the algorithm based on the RC6 accelerated algorithm. Evaluations performed by the synthesis of this method on the FPGA shows that this provides a 21% overhead of approximately 6% increase in hardware resources that cannot be compromised.

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